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CXMT Completes Engineering Sample Validation for Sixth-Generation DRAM Process Platform

October 31, 2026 at 09:39 EDT

Infra & Chips

Chinese memory chipmaker CXMT says it has completed engineering sample validation for its sixth-generation process technology platform, built on a key breakthrough in 4F² vertical-channel dynamic random-access memory (DRAM) architecture.

Engineering sample validated · CXMT

A 4F² vertical-channel DRAM platform clears its first validation step

CXMT reports that engineering samples of its sixth-generation process platform have been validated, built on a vertical-channel DRAM architecture with a 4F² cell layout. The result confirms the design works as intended; yield, capacity and mass-production timing have not yet been disclosed.

4F²

Cell layout based on minimum feature size F

6th

Generation of the process technology platform

Samples

Prototype stage: design confirmed working

Not yet

Yield, capacity and production timeline disclosed

Cell footprint: what 4F² means

Each cell is drawn in units of the minimum feature size F. A 4F² cell covers four F×F squares (2F × 2F).

1F²

= 4F² total cell area, built from four minimum-size squares.

Smaller cell footprints allow more memory per unit of chip area, which is the basic route to higher density and lower cost per bit.

From design to production: where the platform stands

Completed and open steps in the development path.

Vertical-channel design

Architecture

→

4F² cell layout

Core breakthrough

→

Engineering samples validated

Done

→

Yield and performance data

Not disclosed

→

Volume production

No timeline given

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