Google has announced two new chips in its Tensor Processing Unit line, the TPU 8tx and the TPU 8i Max, with each aimed at a distinct stage of AI workloads: large-scale model training and low-latency inference.
Google · Eighth-generation TPU
Google splits its new TPU line into two chips: one to train models, one to serve them
The TPU 8tx targets large-scale training, and the TPU 8i Max targets low-latency inference. The pairing points to a sector-wide shift toward dividing AI hardware by workload stage.
The AI workload pipeline, and where each chip fits
Stage 1
Train models
Large-scale model training
TPU 8tx
→
Stage 2
Serve responses
Real-time inference after training
TPU 8i Max
→
Outcome
Agents in daily use
Agents that respond quickly while handling sensitive data
TPU 8tx
Built for training
Designed for large-scale model training
Positioned for regulated enterprises and governments
Aimed at customers running models and agents on sensitive information
TPU 8i Max
Built for inference
Designed for low-latency inference
Serves model responses in real time after training
Supports day-to-day operation of deployed AI systems
What is still unknown
The positioning is clear. The performance data is not yet public.
Performance figures
Not disclosed
Memory specs
Not disclosed
Pricing and availability
Not disclosed
Independent benchmarks
Not disclosed
Why it matters
The launch extends Google's custom silicon strategy into its eighth TPU generation. Separate chips for training and inference reflect rising demand for both model-building capacity and serving throughput across the sector.
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